Shift registers are core circuit units of integrated circuits that are used in thin film transistor liquid crystal displays (TFT-LCDs). A shift register provides sequential pulse signals to scanning lines of a TFT LCD, so as to control on or off states of TFTs connected to the scanning lines.
Referring to FIG. 5, this is a circuit diagram of a shift register unit 100 of a typical shifter register. The shift register unit 100 includes a first clock inversion circuit 110, an inverter 120, and a second clock inversion circuit 130. All transistors in the first clock inversion circuit 110, the inverter 120, and the second clock inversion circuit 130 are PMOS (P-channel metal oxide semiconductor) transistors. The first clock inversion circuit 110 receives an output signal as a start signal VS from the pre-stage shift register unit (not shown), with the detailed circuit of the first clock inversion circuit 110 described in the following.
The first clock inversion circuit 110 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first output VO1, and a second output VO2. The first transistor M1 includes a gate for receiving the start signal VS, a source coupled to a first voltage (VDD), such as a power voltage, and a drain coupled to a source of the second transistor M2. The second transistor M2 includes a gate and a drain both coupled to a second voltage (VSS), such as a grounding voltage. The third transistor M3 includes a source coupled to the source of the second transistor M2, a drain serving as a first output, and a gate coupled to a gate of the fourth transistor M4. The gates of the third and fourth transistors M3 and M4 serve as a control terminal to receive a clock signal TS. The fourth transistor M4 includes a source coupled to a start signal VS, and a drain serving as a second output.
The inverter 120 includes a fifth transistor M5 and a sixth transistor M6. The inverter 120 outputs an output signal that serves as the shift register signal VO. The fifth transistor M5 includes a source coupled to the first voltage VDD, a gate coupled to the drain of the third transistor M3, and a drain coupled to a source of the sixth transistor M6. The drain of the fifth transistor M5 and the source of the sixth transistor M6 serve as an output for outputting the shift register signal VO. The sixth transistor M6 further includes a gate coupled to the drain of the fourth transistor M4, and a drain coupled to the second voltage VSS.
The second clock inversion circuit 130 and the first clock inversion circuit 120 have the similar structure. The second clock inversion circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The seventh transistor M7 includes a gate for receiving the output signal VO from the inverter 12, a source coupled to the first voltage VDD, and a drain coupled to the a source of the PMOS transistor M8. The eighth transistor M8 further includes a gate and a drain coupled to the second voltage VSS. The ninth transistor M9 includes a source coupled to the source of the eighth transistor M8, a gate coupled to a gate of the tenth transistor M10, and a drain coupled to the gate of the fifth transistor M5. The gates of the ninth and tenth transistors M9 and M10 serve as a control terminal for receiving an inverse clock signal TS. The tenth transistor M10 further includes a source coupled to the gate of the seventh transistor M7 and the shift register signal VO of the inverter 120, and a drain coupled to the gate of the sixth transistor M6 for serving as a second output.
Referring to FIG. 6, this is a sequence waveform diagram of pulse signals of the shift register unit 100. During period t1, the third and fourth transistors M3 and M4 are switched off and the ninth and tenth transistors M9 and M10 are switched on because the start signal VS jumps to a low voltage and the clock signal TS jumps to a high voltage. Thus, the inverter 120 and the second clock inversion circuit 130 perform latch operation. The sixth transistor M6 is switched off such that the shift register signal VO of the inverter 120 keeps an original state of the previous stage.
During period t2, the third and fourth transistors M3 and M4 are switched on and the ninth and tenth transistors M9 and M10 are switched off because the clock signal TS jumps to a low voltage and the inverse clock signal TS jumps to a high voltage. Thus, there is no latch operation. The start signal VS is applied to the inverter 120, and the inverter 120 and the second clock inversion circuit 130 keep the same state as the start signal VS. Further, the first transistor M1 is switched on because the start signal VS jumps to a low voltage, such that the fifth transistors M5 is switched off and the sixth transistor M6 is switched on. Thus, the inverter 120 outputs the shift register signal VO having a low level through the activated sixth transistor M6.
During period t3, the third and fourth transistors M3 and M4 are switched off and the ninth and tenth transistors M9 and M10 are switched on because the clock signal TS jumps to a high voltage and the inverse clock signal TS jumps to a low voltage. Thus, the inverter 120 and the second clock inversion circuit 130 perform latch operation. Thus, the shift register signal VO of the inverter 120 keeps an original state in period t2. The seventh transistor M7 is switched on by the shift register signal VO from the inverter 120, such that the PMOS transistor M5 is still off. In addition, the sixth transistor M6 maintains on state because the shift register signal VO is low-level. Thus, the inverter 120 maintains output of a low level shift register signal VO through the activated sixth transistor M6.
During period t4, the third and fourth transistors M3 and M4 are switched on and the ninth and tenth transistors M9 and M10 are switched off because the clock signal TS jumps to a low voltage and the inverse clock signal TS jumps to a high voltage. Thus, there is no latch operation. The start signal VS is applied to the inverter 120. The inverter 120 and the second clock inversion circuit 130 keep the same state as the start signal VS. The sixth and first transistors M6 and M1 are switched off and the fifth transistor M5 is switched on because the start signal VS is high level. Thus, the inverter 120 stops output of a low-level shift register signal VO.
However, the shift register unit 100 outputs a low level shift register signal during period t2, and at the same time, the next-stage shift register unit (not shown) also outputs a low level shift register signal. Thus, the adjacent shift register units may cause a conflict of signal outputting due to the overlapping of the adjacent shift register signals. Therefore, the shift register is unstable. Accordingly, an LCD device using the shift register has impaired display quality because adjacent columns or rows may be scanned simultaneously.
What is needed, therefore, is a shift register which can overcome the above-described deficiencies. What is also needed is an LCD device including the shift register.